Official duties:
- Support and optimization of existing and maintenance of new developments
- Participation in architectures development, functional schemes development
- Participation in tests and trials, primary launch
- Algorithms development
- Coding of developed and standard FPGAs algorithms
- Testbench development
- Analysis, simulation and calculation of tasks associated with the development
- Maintaining the documentation of reused IP blocks and modules
- Preparation of documentation for transfer to the technical literature department
Requirements:
- Higher profile education, work experience from 2 years
- English – reading technical literature, business correspondence
- Enthusiasm and interest in the work
Required knowledge and skills:
- Fundamentals of digital signal processing
- Programming languages Verilog, SystemVerilog
- Basic knowledge of probability theory and mat statistics
- Radio engineering
- Features of high-speed circuits
- Principles of designing synchronous digital logic
- Modern high-speed interfaces
- Calculation of the computing systems performance
- Simulation of logic circuits
- Work with various microcontrollers and soft processors
- Using version control systems (SVN, Git)
Accomplished skills:
- Working with technology recommendations and standards
- Working with CCD and CMOS sensors
- Experience with Altera’s FPGA
Conditions:
- Schedule of work – regular
- Place of work: railway station Ovrazhki, Malakhovka, Luberetskiy district, Moscow region
